View AS8C403625-QC75N_7741644.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

september 2010 dsc-5280/08 1 . features 128k x 36, 256k x 18 memory configurations supports fast access times: commercial: ? 7.5ns up to 117mhz clock frequency lbo input selects interleaved or linear burst mode self-timed write cycle with global write control ( gw ), byte write enable ( bwe ), and byte writes ( bw x) 3.3v core power supply power down controlled by zz input 3.3v i/o optional - boundary scan jtag interface (ieee 1149.1 compliant) packaged in a jedec standard 100-pin plastic thin quad flatpack (tqfp), pin description summary note: 1. bw 3 and bw 4 are not applicable for the as8c401825. description theas8c403625/1825 are high-speed srams organized as 128k x 36/256k x 18. the as8c403625/1825 srams contain write, data, address and control registers. there are no registers in the data output path (flow-through architecture). internal logic allows the sram to gen- erate a self-timed write based upon a decision which can be left until the end of the write cycle. the burst mode feature offers the highest level of performance to the system designer, as the as8c403625/1825 can provide four cycles of data for a single address presented to the sram. an internal burst address counter accepts the first cycle address from the processor, initiating the access sequence. the first cycle of output data will flow-through from the array after a clock-to-data access time delay from the rising clock edge of the same cycle. if burst mode operation is selected ( adv =low), the subsequent three cycles of output data will be available to the user on the next three rising clock edges. the order of these three addresses are defined by the internal burst counter and the lbo input pin. the as8c403625/1825 srams utilize idt?s latest high-performance cmos process and are packaged in a jedec standard 14mm x 20mm 100-pin thin plastic quad flatpack (tqfp) a 0 -a 17 address inputs input synchronous ce chip enable input synchronous cs 0 , cs 1 chip selects input synchronous oe output enable input asynchronous gw global write enable input synchronous bwe byte write enable input synchronous bw 1 , bw 2 , bw 3 , bw 4 (1) individual byte write selects input synchronous clk clo ck input n/a adv burst address advance input synchronous adsc address status (cache controller) input synchronous adsp address status (processor) input synchronous lbo linear / interleaved burst order input dc tms test mode select input synchronous tdi test data input input synchronous tck test clock input n/a tdo test data output output synchronous trst jtag reset (optional) input asynchronous zz sleep mode input asynchronous i/o 0 -i/o 31 , i/o p1 -i/o p4 data input / output i/o synchronous v dd , v ddq core powe r, i/o po wer supply n/a v ss ground supply n/a 5280 tbl 01 128k x 36, 256k x 18 3.3v synchronous srams 3.3v i/o, flow-through outputs burst counter, single cycle deselect as8c403625 as8c401825
6.42 2 as8c403625, as8c401825, 128k x 36, 256k x 18, 3.3v synchronous srams with 3.3v i/o, flow-through outputs, burst counter, single cycle deselect commercial temperature range pin definitions (1) note: 1. all synchronous inputs must meet specified setup and hold times with respect to clk. symbol pin function i/o active d escription a 0 -a 17 address inputs i n/a synchronous address inputs. the address register is triggered by a combi-nation of the rising edge of clk and adsc low or adsp low and ce low. adsc address status (cache controller) i low synchronous address status from cache controller. adsc is an active low input that is used to load the address registers with new addresses. adsp address status (processor) i low synchronous address status from processor. adsp is an active low input that is used to load the address registers with new addresses. adsp is gated by ce . adv burst address advance i low synchronous address advance. adv is an active low input that is used to advance the internal burst counter, controlling burst access after the initial address is loa ded. when the input is high the burst counter is not incremented; that is, there is no address advance. bwe byte write enable i low synchronous byte write enable gates the byte write inputs bw 1 - bw 4 . if bwe is low at the rising edge of clk then bw x inputs are passed to the next stage in the circuit. if bwe is high then the byte write inputs are blocked and only gw can initiate a write cycle. bw 1 - bw 4 individual byte write enables i low synchronous byte write enables. bw 1 controls i/o 0-7 , i/o p1 , bw 2 controls i/o 8-15 , i/o p2 , etc. any active byte write causes all outputs to be disabled. ce chip enable i low synchronous chip enable. ce is used with cs 0 and cs 1 to enable as8c403625/1825 . ce al so gates adsp . clk c lock i n/a this is the clock input. all timing references for the device are made with respect to this input. cs 0 chip select 0 i high synchronous active high chip select. cs 0 is used with ce and cs 1 to enable the chip. cs 1 chip select 1 i low synchronous active low chip select. cs 1 is used with ce and cs 0 to enable the chip. gw global write enable i low synchronous global write enable. this input will write all four 9-bit data bytes when low on the rising edge of clk. gw supersedes individual byte write enables. i/o 0 -i/o 31 i/o p1 -i/o p4 data input/output i/o n/a synchronous data input/output (i/o) pins. the data input path is registered, triggered by the rising edg e of clk. the data output path is flow-through (no output register). lbo linear burst order i low asy nchronous burst order selection input. when lbo is high, the inter-leaved burst sequence is selected. when lbo is low the linear burst sequence is selected. lbo is a static input and must not change state while the device is operating. oe output enable i low asynchronous output enable. when oe is low the data output drivers are enabled on the i/o pins if the chip is also selected. when oe is high the i/o pins are in a high-impedance state. tms test modeselect i n/a gives input command for tap controller. sampled on rising edge of tdk. this pin has an internal pullup. tdi test data input i n/a serial input of registers placed between tdi and tdo. sampled on rising edge of tck. this pin has an internal pullup. tck test clock i n/a clock input of tap controller. each tap event is clocked. test inputs are captured on rising edge of tck, while test outputs are driven from the falling e dge of tck. this pin has an internal pullup. tdo test dataoutput o n/a serial output of registers placed between tdi and tdo. this output is active depending on the state of the tap controller. trst jtag reset (optional) ilow optional asynchronous jtag reset. can be used to reset the tap controller, but not required. jtag reset occurs automatically at power up and also resets using tms and tck per ieee 1 149.1. if not used trst can be left floating. this pin has an internal pullup. only available in bga package. zz sleep mode i high asynchronous sleep mode input. zz high w ill gate the clk internally and power down the as8c403625/1825 to it s lowest power consumption level. data retention is guaranteed in sleep mode.this pin has an internal pull down. v dd power supply n/a n/a 3.3v core power supply. v ddq power supply n/a n/a 3.3v i/o supply. v ss ground n/a n/a ground. nc no connect n/a n/a nc pins are not electrically connected to the device. 5280 tbl 02
6.42aa as8c403625, as8c401825, 128k x 36, 256k x 18, 3.3v synchronous srams with 3.3v i/o, flow-through outputs, burst counter, single cycle deselect commercial temperature range 3 functional block diagram a 0- a 16/17 address register clr a1* a0* 17/18 2 17/18 a 2- a 17 128k x 36/ 256k x 18- bit memory array internal address a 0 ,a 1 bw 4 bw 3 bw 2 bw 1 byte 1 write register 36/18 36/18 adsp adv clk adsc cs 0 cs 1 byte 1 write driver byte 2 write driver byte 3 write driver byte 4 write driver byte 2 write register byte 3 write register byte 4 write register 9 9 9 9 gw ce bwe lbo i/o 0 -i/o 31 i/o p1 - i/o p4 oe data input register 36/18 output buffer d q enable register oe burst sequence cen clk en clk en q1 q0 2 burst logic binary counter 5280 drw 01 zz powerdown , jtag (sa version) tms tdi tck trst (optional) tdo
6.42 4 as8c403625, as8c401825 128k x 36, 256k x 18, 3.3v synchronous srams with 3.3v i/o, flow-through outputs, burst counter, single cycle deselect commercial temperature range 100 pin tqfp capacitance (t a = +25 c, f = 1.0mhz) recommended operating temperature supply voltage absolute maximum ratings (1) notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. v dd terminals only. 3. v ddq terminals only. 4. input terminals only. 5. i/o terminals only. 6. this is a steady-state dc parameter that applies after the power supplies have ramped up. power supply sequencing is not necessary; however, the voltage on any input or i/o pin cannot exceed v ddq during power supply ramp up. 7. t a is the "instant on" case temperature. recommended dc operating conditions notes: 1. v ih (max) = v ddq + 1.0v for pulse width less than t cyc/2 , once per cycle. 2. v il (min) = -1.0v for pulse width less than t cyc/2 , once per cycle. note: 1. this parameter is guaranteed by device characterization, but not production tested. symbol rating commercial & industrial values unit v te rm (2 ) terminal voltage with respect to gnd -0.5 to +4.6 v v te rm (3,6) terminal voltage with respect to gnd -0.5 to v dd v v te rm (4,6) terminal voltage with respect to gnd -0.5 to v dd +0.5 v v te rm (5,6) terminal voltage with respect to gnd -0.5 to v ddq +0.5 v t a (7) commercial operating temperature -0 to +70 o c industrial operating temperature -40 to +85 o c t bias temperature under bias -55 to +125 o c t stg storage temperature -55 to +125 o c p t power dissipation 2.0 w i out dc output current 50 ma 5 280 tbl 03 grade temperature (1) v ss v dd v ddq commercial 0c to +70c 0v 3.3v5% 3.3v5% industrial -40c to +85c 0v 3.3v5% 3.3v5% 5 280 tbl 04 symbol parameter min. typ. max. uni t v dd core supply voltage 3.135 3.3 3.465 v v ddq i/o supply voltage 3.135 3.3 3.465 v v ss supply voltage 0 0 0 v v ih input high voltage - inputs 2.0 ____ v dd +0.3 v v ih input high voltage - i/o 2.0 ____ v ddq +0.3 (1) v v il input low voltage -0.3 (2 ) ____ 0.8 v 5280 tbl 06 symbol parameter (1 ) conditions max. unit c in input capacitance v in = 3dv 5 pf c i/o i/o capacitance v out = 3dv 7 pf 5280 tbl 07 notes: 1. t a is the "instant on" case temperature. 119 bga capacitance (t a = +25 c, f = 1.0mhz) symbol parameter (1 ) conditions max. unit c in input capacitance v in = 3dv 7 pf c i/ o i/o capacitance v out = 3dv 7 pf 5280 tbl 07a 165 fbga capacitance (t a = +25 c, f = 1.0mhz) symbol parameter (1 ) conditions max. unit c in input capacitance v in = 3dv 7 pf c i/o i/o capacitance v out = 3dv 7 pf 5280 tbl 07b
6.42 idt71v3577, idt71v3579, 128k x 36, 256k x 18, 3.3v synchronous srams with 3.3v i/o, flow-through outputs, burst counter, single cycle deselect commercial and industrial temperature ran ges 5 pin configuration ? 128k x 36 100 tqfp top view notes: 1. pin 14 does not have to be directly connected to v ss as long as the input voltage is < v il . 2. pin 64 can be left unconnected and the device will always remain in active mode. 10099989796959493929190 87868584838281 89 88 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 a 6 a 7 c e c s 0 b w 4 b w 3 b w 2 b w 1 c s 1 v d d v s s c l k g w b w e o e a d s c a d s p a d v a 8 a 9 nc 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 a 1 6 n c l b o a 1 4 a 1 3 a 1 2 a 1 1 a 1 0 v d d v s s a 0 a 1 a 2 a 3 a 4 a 5 i/o p4 i/o 31 i/o 30 v ddq v ss i/o 29 i/o 28 i/o 27 i/o 26 v ss v ddq i/o 25 i/o 24 v ss (1) v dd i/o 23 i/o 22 v ddq v ss i/o 21 i/o 20 i/o 19 i/o 18 v ss v ddq i/o 17 i/o 16 i/o p3 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 i/o p2 i/o 14 v ddq v ss i/o 13 i/o 12 i/o 11 i/o 10 v ss v ddq i/o 9 i/o 8 v ss nc v dd zz (2) i/o 7 i/o 6 v ddq v ss i/o 5 i/o 4 i/o 3 i/o 2 v ss v ddq i/o 1 i/o 0 i/o p1 v ss i/o 15 a 1 5 5280 drw 02a , n c n c n c
6.42 6 idt71v3577, idt71v3579, 128k x 36, 256k x 18, 3.3v synchronous srams with 3.3v i/o, flow-through outputs, burst counter, single cycle deselect commercial and industrial temperature ra nges pin configuration ? 256k x 18 100 tqfp top view notes: 1. pin 14 does not have to be directly connected to v ss as long as the input voltage is < v il . 2. pin 64 can be left unconnected and the device will always remain in active mode. 100 99 98 97 96 95 94 93 92 91 90 87 86 85 84 83 82 81 89 88 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 a 6 a 7 c e c s 0 n c n c b w 2 b w 1 c s 1 v d d v s s c l k g w b w e o e a d s c a d s p a d v a 8 a 9 nc 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 a 1 7 n c n c l b o a 1 5 a 1 4 a 1 3 a 1 2 a 1 1 v d d v s s a 0 a 1 a 2 a 3 a 4 a 5 nc nc nc v ddq v ss nc i/o p2 i/o 15 i/o 14 v ss v ddq i/o 13 i/o 12 v ss v dd i/o 11 i/o 10 v ddq v ss i/o 9 i/o 8 nc nc v ss v ddq nc nc nc 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 a 10 nc v ddq v ss nc i/o p1 i/o 7 i/o 6 v ss v ddq i/o 5 i/o 4 v ss nc v dd zz (2) i/o 3 i/o 2 v ddq v ss i/o 1 i/o 0 nc nc v ss v ddq nc nc nc v ss (1) nc a 1 6 5280 drw 02b , n c n c
as8c403625, as8c401825, 128k x 36, 256k x 18, 3.3v synchronous srams with 3.3v i/o, flow-through outputs, burst counter, single cycle deselect commercial temperature range 7 dc electrical characteristics over the operating temperature and supply voltage range (1) dc electrical characteristics over the operating temperature and supply voltage range (v dd = 3.3v 5%) figure 2. lumped capacitive load, typical derating figure 1. ac test load ac test load ac test conditions (v ddq = 3.3v) note: 1. the lbo , tms, tdi, tck and trst pins will be internally pulled to v dd and the zz in will be internally pulled to v ss if they are not actively driven in the application. notes: 1. all values are maximum guaranteed values. 2. at f = f max, inputs are cycling at the maximum frequency of read cycles of 1/t cyc while adsc = low; f=0 means no input lines are changing. 3. for i/os v hd = v ddq - 0.2v, v ld = 0.2v. for other inputs v hd = v dd - 0.2v, v ld = 0.2v. v ddq /2 50 ? i /o z 0 =50 ? 5280 drw 03 , symbol parameter test conditions min. max. unit |i li | input leakage current v dd = max., v in = 0v to v dd ___ 5a |i li | zz , lbo and jtag input leakage current (1 ) v dd = max., v in = 0v to v dd ___ 30 a |i lo | output leakage current v out = 0v to v ddq , device deselected ___ 5a v ol output low voltage i ol = +8ma, v dd = min. ___ 0.4 v v oh output high voltage i oh = -8ma, v dd = min. 2.4 ___ v 5280 tbl 08 symbol parameter test conditions 7.5ns 8ns 8.5ns unit com'l only com'l ind com'l ind i dd operating power supply current device selected, outputs open, v dd = max., v ddq = max., v in > v ih or < v il , f = f max (2) 255 200 210 180 190 ma i sb1 cmos standby power supply current device deselected, outputs open, v dd = max., v ddq = max., v in > v hd or < v ld , f = 0 (2,3) 30 30 35 30 35 ma i sb2 clock running power supply current device deselected, outputs open, v dd = max., v ddq = max., v in > v hd or < v ld , f = f max (2,.3) 90 85 95 80 90 ma i zz full sleep mode supply current zz > v hd, v dd = max. 30 30 35 30 35 ma 5280 tb l 09 inp ut pulse le ve ls inp ut rise /fall time s inp ut timing re fe re nce le ve ls output timing reference levels ac test load 0 to 3v 2ns 1.5v 1.5v see figure 1 5 280 tbl 10 1 2 3 4 20 30 50 100 200 ? tcd (typical, ns) capacitance (pf) 80 5 6 5280 drw 05 ,
88 as8c403625, as8c401825, 128k x 36, 256k x 18, 3.3v synchronous srams with 3.3v i/o, flow-through outputs, burst counter, single cycle deselect commercial temperature range synchronous truth table (1,3) notes: 1. l = v il , h = v ih , x = don?t care. 2. oe is an asynchronous input. 3. zz - low for the table. operation address used ce cs 0 cs 1 adsp adsc adv gw bwe bw x oe (2 ) clk i/o deselected cycle , po we r do wn no ne h x x x l x x x x x hi-z deselected cycle , po we r do wn no ne l x h l x x x x x x hi-z deselected cycle , po we r do wn no ne l l x l x x x x x x hi-z deselected cycle , po we r do wn no ne l x h x l x x x x x hi-z deselected cycle , po we r do wn no ne l l x x l x x x x x hi-z read cycle, begin burst external l h l l x x x x x l d out read cycle, begin burst external l h l l x x x x x h hi-z read cycle, begin burst external l h l h l x h h x l d out read cycle, begin burst external l h l h l x h l h l d out read cycle, begin burst external l h l h l x h l h h hi-z write cycle, begin burst external l h l h l x h l l x d in write cycle, begin burst external l h l h l x l x x x d in read cycle, continue burst next x x x h h l h h x l d out read cycle, continue burst next x x x h h l h h x h hi-z read cycle, continue burst next x x x h h l h x h l d out read cycle, continue burst next x x x h h l h x h h hi-z read cycle, continue burst next h x x x h l h h x l d out read cycle, continue burst next h x x x h l h h x h hi-z read cycle, continue burst next h x x x h l h x h l d out read cycle, continue burst next h x x x h l h x h h hi-z write cycle, continue burst next x x x h h l h l l x d in write cycle, continue burst next x x x h h l l x x x d in write cycle, continue burst next h x x x h l h l l x d in write cycle, continue burst next h x x x h l l x x x d in read cycle, suspend burst current x x x h h h h h x l d out read cycle, suspend burst current x x x h h h h h x h hi-z read cycle, suspend burst current x x x h h h h x h l d out read cycle, suspend burst current x x x h h h h x h h hi-z read cycle, suspend burst current h x x x h h h h x l d out read cycle, suspend burst current h x x x h h h h x h hi-z read cycle, suspend burst current h x x x h h h x h l d out read cycle, suspend burst current h x x x h h h x h h hi-z write cycle, suspend burst current x x x h h h h l l x d in write cycle, suspend burst current x x x h h h l x x x d in write cycle, suspend burst current h x x x h h h l l x d in write cycle, suspend burst current h x x x h h l x x x d in 5280 tbl 11
9 as8c403625, as8c401825, 128k x 36, 256k x 18, 3.3v synchronous srams with 3.3v i/o, flow-through outputs, burst counter, single cycle deselect commercial temperature range 9 linear burst sequence table ( lbo =v ss ) synchronous write function truth table (1, 2) asynchronous truth table (1) interleaved burst sequence table ( lbo =v dd ) notes: 1. l = v il , h = v ih , x = don?t care. 2. bw 3 and bw 4 are not applicable for the as8c401825. 3. multiple bytes may be selected during the same cycle. notes: 1. l = v il , h = v ih , x = don?t care. 2. synchronous function pins must be biased appropriately to satisfy operation requirements. note: 1. upon completion of the burst sequence the counter wraps around to its initial state. note: 1. upon completion of the burst sequence the counter wraps around to its initial state. operation gw bwe bw 1 bw 2 bw 3 bw 4 r e a d hhxxxx r e a d hl hhhh w r i t e a l l b y t e s lxxxxx w r i t e a l l b y t e s hlllll write byte 1 (3 ) hl l hhh write byte 2 (3 ) hlhlhh write byte 3 (3 ) hlhhlh write byte 4 (3 ) hl hhhl 52 80 tbl 12 operation (2) oe zz i/o status power read l l data out active read h l high-z active write x l hig h-z ? data in active deselected x l high-z standby sleep mode x h high-z sleep 52 80 tbl 13 sequence 1 sequence 2 sequence 3 sequence 4 a1 a0 a1 a0 a1 a0 a1 a0 first address 00011011 second address 0 1 0 0 1 1 1 0 third address 1 0 1 1 0 0 0 1 fourth address (1) 11100100 52 80 tbl 14 sequence 1 sequence 2 sequence 3 sequence 4 a1 a0 a1 a0 a1 a0 a1 a0 first address 00011011 second address 0 1 1 0 1 1 0 0 third address 1 0 1 1 0 0 0 1 fourth address (1) 11000110 52 80 tbl 15
6.42 10 as8c403625,as8c401825, 128k x 36, 256k x 18, 3.3v synchronous srams with 3.3v i/o, flow-through outputs, burst counter, single cycle deselect commercial temperature range ac electrical characteristics (v dd = 3.3v 5%, commercial and industrial temperature ranges) 7.5ns (5) 8ns 8.5ns symbol parameter min.max.min.max.min.max.unit clock parameter t cy c clock cycle time 8.5 ____ 10 ____ 11. 5 ____ ns t ch (1) clock high pulse width 3 ____ 4 ____ 4.5 ____ ns t cl (1 ) clock low pulse width 3 ____ 4 ____ 4.5 ____ ns output parameters t cd clock high to valid data ____ 7.5 ____ 8 ____ 8.5 ns t cd c clock high to data change 2 ____ 2 ____ 2 ____ ns t cl z (2) clock high to output active 0 ____ 0 ____ 0 ____ ns t chz (2 ) clock high to data high-z 2 3.5 2 3.5 2 3.5 ns t oe output enable access time ____ 3.5 ____ 3.5 ____ 3.5 ns t ol z (2) output enable low to output active 0 ____ 0 ____ 0 ____ ns t ohz (2 ) outp ut enable high to output high-z ____ 3.5 ____ 3.5 ____ 3.5 ns set up times t sa address setup time 1.5 ____ 2 ____ 2 ____ ns t ss address status setup time 1.5 ____ 2 ____ 2 ____ ns t sd data in setup time 1.5 ____ 2 ____ 2 ____ ns t sw write se tup time 1.5 ____ 2 ____ 2 ____ ns t sav address advance setup time 1.5 ____ 2 ____ 2 ____ ns t sc chip enable/select setup time 1.5 ____ 2 ____ 2 ____ ns hold times t ha address hold time 0.5 ____ 0.5 ____ 0.5 ____ ns t hs address status hold time 0.5 ____ 0.5 ____ 0.5 ____ ns t hd data in hold time 0.5 ____ 0.5 ____ 0.5 ____ ns t hw write hold time 0.5 ____ 0.5 ____ 0.5 ____ ns t hav address advance hold time 0.5 ____ 0.5 ____ 0.5 ____ ns t hc chip enable/select hold time 0.5 ____ 0.5 ____ 0.5 ____ ns sleep mode and configuration parameters t zzp w zz pulse width 100 ____ 100 ____ 100 ____ ns t zzr (3) zz recovery time 100 ____ 100 ____ 100 ____ ns t cfg (4) configuration set-up time 34 ____ 40 ____ 50 ____ ns 5280 tbl 16 notes: 1. measured as high above v ih and low below v il . 2. transition is measured 200mv from steady-state. 3. device must be deselected when powered-up from sleep mode. 4. t cfg is the minimum time required to configure the device based on the lbo input. lbo is a static input and must not change during normal operation. 5. commercial temperature range only.
6.42 idt71v3577, idt71v3579, 128k x 36, 256k x 18, 3.3v synchronous srams with 3.3v i/o, flow-through outputs, burst counter, single cycle deselect commercial and industrial temperature ran ges 13 notes: 1. o1 (ax) represents the first output from the external address ax. o1 (ay) represents the first output from the external address ay; o2 (ay) represents the next output data in the burst sequence of the base address ay, etc. where a0 and a1 are advancing for the four word burst in the sequence defined by the state of the lbo input. 2. zz input is low and lbo is don't care for this cycle. 3. cs 0 timing transitions are identical but inverted to the ce and cs 1 signals. for example, when ce and cs 1 are low on this waveform, cs 0 is high. timing waveform of flow-through read cycle (1,2) t c h z t s a t s c t h s g w , b w e , b w x t s w t c l t s a v t h w t h a v c l k a d s p a d s c ( 1 ) a d d r e s s t c y c t c h t h a t h c t o e t o h z o e t c d t o l z o 1 ( a x ) d a t a o u t t c d c o 1 ( a y ) o 2 ( a y ) o 2 ( a y ) a d v c e , c s 1 ( n o t e 3 ) f lo w - t h r o u g h r e a d b u r s t f lo w - t h r o u g h r e a d o u t p u t d is a b le d a x a y t s s o 1 ( a y ) o 4 ( a y ) o 3 ( a y ) ( b u r s t w r a p s a r o u n d t o it s in it ia l s t a te ) 5 2 8 0 d r w 0 6 a d v h i g h s u s p e n d s b u r s t ,
6.42 14 idt71v3577, idt71v3579, 128k x 36, 256k x 18, 3.3v synchronous srams with 3.3v i/o, flow-through outputs, burst counter, single cycle deselect commercial and industrial temperature ra nges o 1 ( a z ) c l k a d s p a d d r e s s g w a d v o e d a t a o u t t c y c t c h t c l t h a t s w t h w t c l z a x a y a z t h s i1 ( a y ) t s d t h d t o l z t c d t c d c d a t a i n ( 2 ) t o e o 1 ( a z ) s in g le r e a d f lo w - th r o u g h b u r s t r e a d w r ite t o h z t s s t s a o 3 ( a z ) o 2 ( a z ) o 4 ( a z ) o 1 ( a x ) 5 2 8 0 d r w 0 7 t c d , notes: 1. device is selected through entire cycle; ce and cs 1 are low, cs 0 is high. 2. zz input is low and lbo is don't care for this cycle. 3. o1 (ax) represents the first output from the external address ax. i1 (ay) represents the first input from the external address ay; o1 (az) represents the first output from the external address az; o2 (az) represents the next output data in the burst sequence of the base address az, etc. where a0 and a1 are advancing for the four word burst in the sequence defined by the state of the lbo input. timing waveform of combined flow-through read and write cycles (1,2,3)
6.42 idt71v3577, idt71v3579, 128k x 36, 256k x 18, 3.3v synchronous srams with 3.3v i/o, flow-through outputs, burst counter, single cycle deselect commercial and industrial temperature ran ges 15 timing waveform of write cycle no. 1 - gw controlled (1,2,3) a d d r e s s c l k a d s p a d s c t c y c t s s t h s t c h t c l t h a t s a a x a y a z a d v d a t a o u t o e t h c t s d i1 ( a x ) i1 ( a z ) i2 ( a y ) th d t o h z d a t a i n t h a v o 4 ( a w ) c e , c s 1 t h w g w t s w ( n o t e 3 ) i 2 ( a z ) i3 ( a z ) i4 ( a y ) i3 ( a y ) i2 ( a y ) t s a v ( a d v s u s p e n d s b u r s t ) i1 ( a y ) t s c ( 1 ) ( 2 ) o 3 ( a w ) 5 2 8 0 d r w 0 8 g w is ig n o r e d w h e n a d s p in itia te s a c y c le a n d is s a m p le d o n th e n e x t c y c le r is in g e d g e , notes: 1. zz input is low, bwe is high and lbo is don't care for this cycle. 2. o4 (aw) represents the final output data in the burst sequence of the base address aw. i1 (ax) represents the first input from the external address ax. i1 (ay) represents the first input from the external address ay; i2 (ay) represents the next input data in the burst sequence of the base address ay, etc. where a0 and a1 are advancing for the four word burst in the sequence defined by the state of the lbo input. in the case of input i2 (ay) this data is valid for two cycles because adv is high and has suspended the burst. 3. cs 0 timing transitions are identical but inverted to the ce and cs 1 signals. for example, when ce and cs 1 are low on this waveform, cs 0 is high.
6.42 16 idt71v3577, idt71v3579, 128k x 36, 256k x 18, 3.3v synchronous srams with 3.3v i/o, flow-through outputs, burst counter, single cycle deselect commercial and industrial temperature ra nges timing waveform of write cycle no. 2 - byte controlled (1,2,3) a d d r e s s c l k a d s p a d s c t c y c t s s t h s t c h t c l t h a t s a a x a y t h w b w x a d v d a t a o u t o e t h c t s d s in g le w r ite b u r s t w r ite i1 ( a x ) i2 ( a y ) i 2 ( a y ) i2 ( a z ) t h d b u r s t r e a d e x te n d e d b u r s t w r ite t o h z d a t a i n t s a v t s w o 4 ( a w ) c e , c s 1 t h w b w e t s w ( n o te 3 ) i 1 ( a z ) a z i4 ( a y ) i1 ( a y ) i4 ( a y ) i3 ( a y ) t s c b w e is ig n o r e d w h e n a d s p in it ia t e s a c y c le a n d is s a m p le d o n t h e n e x t c y c le r is in g e d g e b w x is ig n o r e d w h e n a d s p in itia t e s a c y c le a n d is s a m p le d o n t h e n e x t c lo c k r is in g e d g e i 3 ( a z ) o 3 ( a w ) 5 2 8 0 d r w 0 9 ( a d v h i g h s u s p e n d s b u r s t ) , notes: 1. zz input is low, gw is high and lbo is don't care for this cycle. 2. o4 (aw) represents the final output data in the burst sequence of the base address aw. i1 (ax) represents the first input from the external address ax. i1 (ay) represents the first input from the external address ay; i2 (ay) represents the next input data in the burst sequence of the base address ay, etc. where a0 and a1 are advancing for the four word burst in the sequence defined by the state of the lbo input. in the case of input i2 (ay) this data is valid for two cycles because adv is high and has suspended the burst. 3. cs 0 timing transitions are identical but inverted to the ce and cs 1 signals. for example, when ce and cs 1 are low on this waveform, cs 0 is high.
6.42 idt71v3577, idt71v3579, 128k x 36, 256k x 18, 3.3v synchronous srams with 3.3v i/o, flow-through outputs, burst counter, single cycle deselect commercial and industrial temperature ran ges 17 t c y c t s s t c l t c h t h a t s a t s c t h c t o e t o l z t h s c l k a d s p a d s c a d d r e s s g w c e , c s 1 a d v d a t a o u t o e z z s in g le r e a d s n o o z e m o d e tz z p w 5 2 8 0 d r w 1 3 o 1 ( a x ) a x ( n o t e 4 ) tz z r a z , notes: 1. device must power up in deselected mode. 2. lbo is don't care for this cycle. 3. it is not necessary to retain the state of the input registers throughout the power-down cycle. 4. cs 0 timing transitions are identical but inverted to the ce and cs 1 signaals. for example, when ce and cs 1 are low on this waveform, cs 0 is high. timing waveform of sleep (zz) and power-down modes (1,2,3)
16 as8c403625, as8c401825, 128k x 36, 256k x 18, 3.3v synchronous srams with 3.3v i/o, flow-through outputs, burst counter, single cycle deselect commercial temperature range notes: 1. zz input is low, adv is high and lbo is don't care for this cycle. 2. (ax) represents the data for address ax, etc. 3. for read cycles, adsp and adsc function identically and are therefore interchangable. non-burst read cycle timing waveform clk adsp gw , bwe , bw x ce , cs 1 cs 0 address adsc data out oe av aw ax ay az (av) (aw) (ax) (ay) 5280 drw 10 , non-burst write cycle timing waveform clk adsp gw ce , cs 1 cs 0 address adsc data in av aw ax az ay (av) (aw) (ax) (az) (ay) 5280 drw 11 , notes: 1. zz input is low, adv and oe are high, and lbo is don't care for this cycle. 2. (ax) represents the data for address ax, etc. 3. although only gw writes are shown, the functionality of bwe and bw x together is the same as gw . 4. for write cycles, adsp and adsc have different limitations.
17717172 as8c403625, as8c401825, 128k x 36, 256k x 18, 3.3v synchronous srams with 3.3v i/o, flow-through outputs, burst counter, single cycle deselect commercial temperature range 17 jtag interface specification (sa version only) tck device inputs (1) / tdi/tms device outputs (2) / tdo trst ( 3) t jcd t jdc t jrst t js t jh t jcyc t jrsr t jf t jcl t jr t jch m5280 drw 01 x symbol parameter min. max. units t jcyc jtag clock input period 100 ____ ns t jch jtag clock high 40 ____ ns t jcl jtag clock low 40 ____ ns t jr jtag clock rise time ____ 5 (1) ns t jf jtag clock fall time ____ 5 (1) ns t jrst jtag reset 50 ____ ns t jrsr jtag reset recovery 50 ____ ns t jcd jtag data output ____ 20 ns t jdc jtag data output hold 0 ____ ns t js jtag setup 25 ____ ns t jh jtag hold 25 ____ ns i52 80 tbl 01 register name bit size instruction (ir) 4 bypass (byr) 1 jtag identification (jidr) 32 boundary scan (bsr) note (1) i5280 tbl 03 notes: 1. device inputs = all device inputs except tdi, tms and trst . 2. device outputs = all device outputs except tdo. 3. during power up, trst could be driven low or not be used since the jtag circuit resets automatically. trst is an optional jtag reset. note: 1. the boundary scan descriptive language (bsdl) file for this device is available jtag ac electrical characteristics (1,2,3,4) scan register sizes notes: 1. guaranteed by design. 2. ac test load (fig. 1) on external output signals. 3. refer to ac test conditions stated earlier in this document. 4. jtag operations occur at one speed (10mhz). the base device may run at any speed specified in this datasheet.
2 18 as8c403625, as8c401825, 128k x 36, 256k x 18, 3.3v synchronous srams with 3.3v i/o, flow-through outputs, burst counter, single cycle deselect commercial temperature range notes: 1. device outputs = all device outputs except tdo. 2. device inputs = all device inputs except tdi, tms, and trst . instruction field value description revision number (31:28) 0x2 reserved for version number. device id (27:12) 0x22c, 0x22e defines as8c403625/1825 jedec id (11:1) 0x33 allows unique identifi cation of device vendor . id register indicator bit (bit 0) 1 indicates the presence of an id register. i5280 tbl 02 jtag identification register definitions (sa version only) instruction description opcode extest forces contents of the boundary scan cells onto the device outputs (1) . places the boundary scan registe r (bsr) between tdi and tdo. 0000 sample/preload places the boundary scan registe r (bsr) between tdi and tdo. sample allows data from device inputs (2) and outputs (1 ) to be captured in the boundary scan cells and shifted serially through tdo. preload allows data to be input serially into the bo undary scan cells via the tdi. 0001 device_id loads the jtag id register (jidr) with the vendor id code and places the register between tdi and tdo. 0010 highz places the bypass register (byr) between tdi and tdo. forces all device output drivers to a high-z state. 0011 reserved several combinations are reserved. do not use codes other than those identified for extest, sample/preload, device_id, highz, clamp, validate and bypass instructions. 0100 reserved 0101 reserved 0110 reserved 0111 clamp uses byr. forces contents of the boundary scan cells onto the device outputs. places the bypass register (byr) between tdi and tdo. 1000 reserved same as above. 1001 reserved 1010 reserved 1011 reserved 1100 validate automatically loaded into the instruction register whenever the tap controller passes through the capture-ir state. the lower two bits '01' are mand ated by the ieee std. 1149.1 specification. 1101 reserved same as above. 1110 bypass the bypass instruction is used to truncate the boundary scan register as a single bit in length. 1111 i5280 tbl 04 available jtag instructions
192 as8c403625, as8c401825, 128k x 36, 256k x 18, 3.3v synchronous srams with 3.3v i/o, flow-through outputs, burst counter, single cycle deselect commercial temperature range 19 100-pin plastic thin quad flatpack (tqfp) 119 ball grid array (bga) 165 fine pitch ball grid array (fbga) pf** bg bq device type restricted hazardous substance device g alliance organ iza tion vcc range package operating temp speed ns AS8C403625-QC75N 128 k x 36 3.1 - 3.4v 100 pin t qfp comercial 0 - 70c 7.5 as8c401825-qc75n 256k x 18 3.1 - 3.4v 100 pin tqfp comercial 0 - 70c 7.5 ordering information ordering information alliance organ iza tion vcc range package operating temp speed ns as6c8016a -55zin 512k x 16 2.7 - 5.5v 44pin tsop ii industrial ~ -40 c - 85 c 55 as6c8016a -55bin 512k x 16 2.7 - 5.5v 48ball fb ga industrial ~ -40 c - 85 c 55 part numbering system ordering information ordering information alliance organ iza tion vcc range package operating temp speed ns as6c8016a -55zin 512k x 16 2.7 - 5.5v 44pin tsop ii industrial ~ -40 c - 85 c 55 as6c8016a -55bin 512k x 16 2.7 - 5.5v 48ball fb ga industrial ~ -40 c - 85 c 55 part numbering system as6c 8016 -55 x x n device number package option temperature range 80 = 8m z - 44pin tsop i = industrial low power sram prefix 16 = x16 access time b = 48ball tfbga (-40 to + 85 c) n = lead free rohs compliant part part numbering system as8c 01= zbt q = 100 pin tqfp sync. sram prefix 18= x18 36 = x36 25 = flow- thru 0 ~ 70c 7.5 ns n= leadfree 40 = 4m 00 = pipelined speed device conf. mode package operating temp n ? alliance memory, inc. 551 taylor way, suite#1, san carlos , ca 94 070 tel: 650- 610-6800 fax: 650- 620-9211 www.alliancememory.com copyright ? alliance memory all rights reserved part number: as 8c403625/401825 document version: v. 1.0 ? copyright 2003 alliance memory, inc. all rights reserved. our three-point logo, our name and intelliwatt are trademarks or re gistered trademarks of alliance. all other brand and product names may be the trademarks of their respective companies. alliance reserves the right to make changes to this document and its products at any time without notice. alliance assumes no responsibility for any errors that may appear in this document. the data contained herein represents alliance's best data and/or estimates at the time of issuance. alliance reserves the right to chang e or correct this data at any time, without notice. if the product described herein is under development, significant changes to these specifications are pos sible. the information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intende d to operate as, or provide, any guarantee or warrantee to any user or customer. alliance do es not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warra nties related to the sale and/or use of alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, e xcept as express agreed to in alliance's terms and conditions of sale (which are available from alliance). all sales of alliance products are made exclusivel y according to alliance's terms and conditions of sale. the purchase of products from allia nce does not convey a license under any patent rights, copyrig hts; mask works rights, trademarks, or any other intellectual property rights of allianc e or third parties. alliance do es not authorize its products fo r use as critical components in life-supporting systems where a malfunction or failure may reasonabl y be expected to result in significant injury to the user, and the inclusion of alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to inde mnify alliance against all claims arising from such use.

▲Up To Search▲

Price & Availability of AS8C403625-QC75N

	To Download AS8C403625-QC75N Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .